1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a non-volatile memory device, and more particularly, to a method for fabricating a non-volatile memory device including a plurality of memory cells that are stacked in multiple layers on a substrate.
2. Description of the Related Art
A non-volatile memory device retains data although power is turned off. Diverse non-volatile memory devices, such as a NAND-type flash memory device, are widely used.
As a two-dimensional non-volatile memory device where memory cells are formed in a single layer has reached technical limitation in increasing its integration degree, a three-dimensional non-volatile memory device where a plurality of memory cells are stacked in multiple layers on a silicon substrate is suggested.
Three-dimensional non-volatile memory devices of diverse structures are being developed, and among them is a flash memory that is referred to as a PBiCS. A PBiCS flash memory device is well known and disclosed in an article entitled “Pipe-Shaped BiCS Flash Memory with 16 Stacked Layers And Multi-Level-Cell Operation for Ultra-High Density Storage Devices,” VLSI Technology, Jun. 16-18, 2009 symposium, ISBN 978-4-86348-009-4, pp. 136-137. The PBiCS flash memory device is fabricated through a series of processes of forming a pipe gate electrode layer having a sacrificial layer, forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of cell gate electrode layers are alternately stacked over the pipe gate electrode layer, removing the sacrificial layer exposed after memory holes penetrating through the stacked structure are formed, depositing a memory layer having a triple-layer structure of oxide-nitride-oxide (ONO) in the memory holes and a space from which the sacrificial layer is removed, and depositing silicon bodies that are used as channels over the memory layer.
When the PBiCS flash memory device is fabricated through the above-described fabrication process, it may have the following features.
When the ONO layer is deposited in the memory holes and the space from which the sacrificial layer is removed, the ONO layer is deposited thinner in the space from which the sacrificial layer is removed than in the memory holes due to step coverage characteristics. When the ONO layer is thin in the space from which the sacrificial layer is removed, breakdown voltage may be so low that it is difficult to apply a high voltage, such as a pass voltage, to the pipe gate electrode layer. This is because the reliability of the PBiCS flash memory device is deteriorated, for example, threshold voltage thereof is increased, when a high voltage is applied to the pipe gate electrode layer.
When the thickness of the ONO layer is increased in overall, the memory holes having a narrow width are filled with the ONO layer and thus the space where the channels are to be formed may not be secured.